Simultaneous reduction of supply and threshold voltages for low-power silicon-on-insulator (SOI) CMOS design without suffering performance losses will eventually reach the limit of diminishing returns as static power dissipation becomes a significant portion of the total power equation. In order to meet the opposing requirements of high-performance during circuit/system active periods, and low-power, during circuit/system idle periods, a dynamic threshold voltage control scheme is needed.
For SOI metal oxide field effect transistors (MOSFETs), there are two modes of operation: 1) fully depleted, and 2) partially depleted channel region. In conventional strongly fully depleted SOI devices, the silicon film thickness is usually less than or equal to half the depletion width of the bulk device. The surface potentials at the front and back interfaces are strongly coupled to each other and capacitively coupled to the front-gate and substrate through the front-gate dielectric and the buried oxide, respectively. Therefore, the potential throughout the silicon film, and hence the charge, is determined by the bias conditions on both the front-gate and the substrate. By replacing the substrate with a back-gate, the device becomes a dual-gated device.
The fully depleted design is unique to SOI because the front-gate and the back-gate both have control of the charge in the silicon film. In the strongly partially depleted device, the back-gate or the substrate has no influence on the front surface potential. In the middle regime, the device is nominally partially depleted and can become fully depleted by applying bias, thus, coupling of the front and back surface potentials still occurs.
To date, no adequate dynamic threshold voltage control schemes are present in conventional SOI MOSFET devices; therefore, as these devices are continually being scaled down to smaller sizes, the devices will become extremely leaky when operating under low-power conditions, i.e., when the devices are idle.
In view of the state of the art mentioned above, there is a continued need for providing a SOI MOSFET device that includes a dynamic threshold voltage control scheme that works under circuit/system active periods, as well as circuit/system idle periods.